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SC-P-026

3차원 적층 기술

Superconducting부품QPU
PRODUCT
3차원 적층 기술

Technical Description

3D stacking involving two-layer flip-chip and three-or-more-layer TSV structures

Specifications

Two-layer structure: room-temperature and low-heat flip-chip fabrication, xy tolerance <1 µm, z tolerance <1 µm
Three-or-more-layer structure: room-temperature and low-heat TSV fabrication, xy tolerance <1 µm, z tolerance <1 µm

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